The integrated circuit industry has, since its inception, maintained a remarkable growth rate by driving increased device functionality at lower cost. Leading edge devices today provide the computing power of computers that used to occupy entire rooms at a mere fraction of the cost. Many of today's low-cost consumer devices include functionality that only a few years ago was unavailable at any cost, such as video cell phones, ultra-portable media players, and wireless or ultra-wideband Internet devices. One of the primary enabling factors of this growth has been the ability of optical lithography processes to steadily decrease the smallest feature size that can be patterned as part of an integrated circuit pattern. This steady decline in feature size and cost while at the same time printing more features per circuit is commonly referred to as “Moore's Law” or the lithography “roadmap.”
The lithography process involves creating a master image on a mask then replicating that pattern faithfully onto the device wafers. The more times a master pattern is successfully replicated within the design specifications, the lower the cost per finished device or “chip.” Until recently, the mask pattern has been an exact duplicate of the desired pattern at the wafer level, with the exception that the mask level pattern may be several times larger than the wafer level pattern. This scale factor is then corrected during wafer exposure by the reduction ratio of the exposure tool. The mask pattern is typically formed by depositing and patterning a light-absorbing material on a quartz or other transmissive substrate. The mask is then placed in an exposure tool known as a “stepper” or “scanner” where light of a specific exposure wavelength is directed through the mask onto the device wafers. The light is transmitted through the clear areas of the mask and attenuated by a desired amount, typically between 90% and 100%, in the areas that are covered by the absorbing layer. The light that passes through some regions of the mask may also be phase-shifted by a desired phase angle, typically an integer multiple of 180 degrees. After being collected by the exposure tool, the resulting aerial image pattern is then focused onto the device wafers. A light sensitive material deposited on the wafer surface interacts with the light to form the desired pattern on the wafer, and the pattern is then transferred into the underlying layers on the wafer to form functional electrical circuits according to well-known processes.
In recent years, the feature sizes being patterned have become significantly smaller than the wavelength of light used to transfer the pattern. This trend towards “sub-wavelength lithography” has resulted in increasing difficulty in maintaining adequate process margins in the lithography process. The aerial images created by the mask and exposure tool lose contrast and sharpness as the ratio of feature size to wavelength decreases. This ratio is quantified by the k1 factor, defined as the numerical aperture of the exposure tool times the minimum feature size divided by the wavelength. Currently, the practical flexibility in choosing the exposure wavelength is limited, and the numerical aperture of exposure tools is approaching physical limits. Consequently, the continuous reduction in device feature sizes requires more and more aggressive reduction of the k1 factor in lithographic processes, i.e., imaging at or below the classical resolution limits of an optical imaging system.
New methods to enable low-k1 lithography have resulted in master patterns on the mask that are not exact copies of the final wafer level patterns. The mask pattern is often adjusted in terms of the size and the location of the pattern as a function of pattern density or pitch. Other techniques involve the addition or subtraction of extra corners on the mask pattern (“serifs,” “hammerheads,” and other patterns), and even the addition of geometries that will not be replicated on the wafer. These non-printing “assist features” may include scattering bars, holes, rings, checkerboards, or “zebra stripes” to change the background light intensity (“gray scaling”), and other structures, which are well documented in the literature. All of these methods are often referred to collectively as “Optical Proximity Correction,” or “OPC.” With decreasing k1, the magnitude of proximity effects increases dramatically. In current high-end designs, more and more device layers require OPC, and almost every feature edge requires some amount of adjustment in order to ensure that the printed pattern will reasonably resemble the design intent. The implementation and verification of such extensive OPC application is only made possible by detailed full-chip computational lithography process modeling, and the process is generally referred to as model-based OPC. (See “Full-Chip Lithography Simulation and Design Analysis—How OPC Is Changing IC Design,” C. Spence, Proc. SPIE, Vol. 5751, pp. 1-14 (2005) and “Exploring New High Speed, Mask Aware RET Verification Flows,” P. Martin et al., Proc. SPIE 5853, pp. 114-123, (2005)).
The mask may also be altered by the addition of phase-shifting regions that may or may not be replicated on the wafer. Many phase-shifting techniques have been described at length in the literature, including alternating aperture shifters, double expose masking processes, multiple phase transitions, and attenuating phase-shifting masks. Masks formed by these methods are known as “Phase-Shifting Masks,” or “PSMs.” All of these techniques to increase image slope and contrast at low-k1, including OPC, PSM, and others, are referred to collectively as “Resolution Enhancement Technologies,” or “RETs.” The result of all of these RETs, which are often applied to the mask in various combinations, is that the final pattern formed at the wafer level is no longer a simple replicate of the mask level pattern. In fact, it is becoming impossible to look at the mask pattern and simply determine what the final wafer pattern is supposed to look like. This greatly increases the difficulty in verifying that the design data is correct before the mask is made and wafers are exposed as well as in verifying that the RETs have been applied correctly and that the mask meets its target specifications.
The proliferation of OPC and other RETs results in a number of considerable challenges. In particular, a post-OPC mask design bears very limited resemblance to the pre-OPC design intent, i.e., the semiconductor structures intended to be manufactured. Even more challenging is a reduction of process windows, i.e., the tolerance of the lithographic process against unintended variations of certain parameters such as exposure dose and focus that accompanies the reduction of k1 factors. Furthermore, as proximity effects are getting more pronounced, the exact behavior of a feature under small changes of process parameters becomes extremely nonlinear and often non-intuitive. Even minor undetected process variations may have significant unpredicted impact on device yields. Such yield loss will most likely occur at “weak points” or “hot spots” of a design and is thus qualitatively different from yield loss resulting from random “point defects” caused by, e.g., mask contamination. At the current state of semiconductor manufacturing, it appears that device yield is increasingly limited by design weaknesses rather than by random defects.
A major contribution to systematic process variations that may push a weak design feature into failure are the exact physical properties of the mask itself. Relevant physical mask parameters may include line-width biases, corner rounding, pitch dependencies due to mask-write or mask-etch proximity effects, anisotropies, phase errors, polarization, birefringence, or in general “3-D mask effects.” These parameters may vary within the area of a single mask, between masks manufactured at different times, masks manufactured on different tools, or masks from different mask shops.
While the OPC and mask design is based on detailed models, the actual physical properties of the mask may differ from the assumptions of the model and thereby may shift process windows and optimum process conditions or cause unexpected yield loss. Such yield loss may occur at previously identified hot spots. However, unanticipated and undetected variations in physical mask parameters may also considerably change the severity of hot spots or even lead to failure of patterns that would not be identified as “marginal” (or “weak”) under nominal conditions. (A “marginal” or “weak” pattern is a pattern that may easily result in failure or yield loss due to, e.g., manufacturing uncertainties or process variations.)
Traditional mask inspection focuses on detecting isolated point defects such as dust particles or pinholes on the mask and thus cannot detect a mask's systematic errors and their impact on process-window related “design defects” or “hot spots.” FIG. 1 is a flowchart of method steps for a prior-art manufacturing process, in which such traditional mask inspection occurs in step 120. In step 110, the pre-OPC design layout showing the design intent for a chip is produced. Then, in step 112, the pre-OPC design layout is processed using OPC and other RETs to produce a post-OPC mask layout. In step 114, the full chip is simulated using a model of the lithography process and a nominal mask error model applied to the post-OPC mask layout to predict the printed patterns. An example of simulating a lithography process using such a lithography process model and mask model is disclosed in “System and Method for Lithography Simulation,” U.S. Pat. No. 7,003,758 (the '758 patent), the subject matter of which is hereby incorporated by reference in its entirety. In step 116, the pre-OPC design layout, i.e., the design intent, is compared against the predicted printed patterns to determine if the post-OPC mask layout is acceptable. If so, the method continues in step 118; if not, the method returns to step 112, where the comparison results from step 116 will be used to tune the post-OPC mask layout to produce a new post-OPC mask layout, and then steps 114 and 116 will be repeated. Once the predicted printed patterns are determined to be acceptable, then the method continues in step 118, in which a mask is manufactured according to the acceptable post-OPC mask layout. Then, in step 120, the mask is inspected to identify isolated point defects such as dust particles or pinholes. In step 122, the identified point defects are evaluated to determine if the manufactured mask is acceptable. If so, the method continues in step 128; if not, the method continues in step 124, in which the mask is evaluated to determine if it is repairable. If the mask is repairable, the method continues in step 126, in which the mask is repaired, and then the method returns to step 120; if the mask is not repairable, then the method returns to step 118, in which a new mask will be manufactured. In optional step 128, the lithography process is tuned using information from the simulations of step 114. Such information may include hot spot reports for targeted wafer inspection or optimized process conditions. However, since the simulations during the design phase are based on nominal conditions (in particular, nominal values for the mask error model parameters), the effectiveness of such feed-forward information will be limited. In step 130, wafers are printed using the manufactured (and maybe also repaired) mask.
As indicated in FIG. 1, a prior art device manufacturing process proceeds from a pre-OPC design layout that defines the desired functionality of a device to a post-OPC mask layout by applying OPC or other RETs. This process of converting a pre-OPC design layout into a post-OPC mask layout currently relies heavily on numerical simulation of the lithography process (e.g., model-based OPC and model-based design verification) and may typically require several iterations before a design is considered acceptable. Full-chip simulation is required to ensure that all elements of the device will print on the wafer as intended. The simulation for OPC generation and design verification may, e.g., use a lithography simulation system as described in the '758 patent, which can predict printed resist or feature contours from a mask layout, taking into account the optical properties of the projection process as well as the properties of the resist layer on a production wafer.
Once the mask layout is determined to be acceptable, a physical mask will be manufactured by a mask shop and delivered to the fab. This mask may be inspected using existing mask inspection tools in order to detect and possibly repair any point defects due to, e.g., any contamination during mask manufacturing. Subsequently, the mask will be loaded into an exposure tool to print production wafers. Notably, while detailed simulation models are a central part of the mask design process, traditionally no model-based information is utilized in the overall lithographic device manufacturing process once the mask has been made. In practice, this situation often leaves the mask manufacturing process open to considerable uncertainties (e.g., whether OPC has been properly implemented on the actual mask). For any new mask, there may also be a need to adjust empirically—essentially by trial-and-error—process parameters in order to produce, e.g., printed line-widths close enough to the design target. Consequently, if any systematic mask errors have been introduced in the mask manufacturing process, it may take a long time and a large number of printed wafers before such errors can be unambiguously detected and corrected.
As a result, there exists a strong need for systems and methods that verify the physical properties of actual lithographic masks and their effects on the pattern printing process, taking into account the design intent. Such methods would enable a predictive and proactive qualification of masks before exposing any wafers and would also enable adjustments or process corrections to optimize printed device yield for a given physical mask. Such process corrections may be identified by accurate modeling and may, for example, involve adjustments of exposure dose, focus offsets, NA-sigma settings, choices among different exposure tools, and, when systematic mask error repair technology is available, feedback to a mask manufacturing process to repair the systematic mask errors.